1. Technical Field
The present invention relates to data processing systems, and more particularly to apparatus for executing instructions which control data flow between a computational subsystem and an I/O subsystem.
2. Background Art
Copending patent application Ser. No. 921,313, now abandoned addresses the basic I/O problem of how to couple two different bus types. On the I/O bus different devices having a spectrum of data rates generated by different peripherals are handled by the bus. Some devices have the added problem of quiet periods followed by very busy periods with sharp transitions between the two. This problem is solved by providing a processor bus sequencer, an I/O bus sequencer, and an execution unit, all of which operate asynchronously and share a common register file memory.
Copending patent application Ser. No. 046,633, U.S. Pat. No. 4,803,622 describes the I/O bus sequencer. The I/O bus sequencer is connected to the I/O bus and to the register file. The register file is uniformly addressed and adapted to be shared by the execution unit, the system bus sequencer and the I/O bus sequencer. The register file is comprised of a plurality of multiported register sets.
The present invention is concerned with the execution unit which controls the remainder of the system described in the above-identified patent applications. In modern VLSI technology, there are limits on clock rate, chip area and power consumption that must be considered in order to achieve high performance. These limits can be dealt with by designing parallelism into the apparatus, and for the execution unit this means the ability to handle several tasks at one time.
It is therefore an object of the present invention to achieve parallelism in an I/O channel processor by providing an execution unit that supports multi-tasking.